Xu Zhang

Computer Science, Ph.D. Candidate

100080, Institute of Computing Technology, Academy South Road, No.6, Beijing, China

Currently

Studying under the supervision of Professor Mingyu Chen,

in Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS).

Research interests

My researches mainly focus on how to mitigate the significant letancy of accessing far memory, which poses an urgent and challenging problem for both Memory Disaggregation System and Distributed Shared-Memory System. I have explored a general hardware approach and a more specialized software approach targeted at Graph Computing.

Education

2019 - 2025 Doctor, Institute of Computing Technology (ICT), CAS

2018 - 2019 Exchange Student, National University of Singapore (NUS)

2015 - 2019 Bachelor, University of Chinese Academy of Sciences (UCAS)

Publications

2024 L. Wang and X. Zhang and S. Wang and Z. Jiang and T. Lu and M. Chen and S. Luo and K. Huang, “Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access,” accepted by ACM Transactions on Architecture and Code Optimization (TACO). paper

2023 X. Zhang, T. Lu, Y. Chang, K. Zhang and M. Chen, “Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory,” 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington, DC, USA, 2023, pp. 134-141, doi: 10.1109/ICCD58817.2023.00029. paper, slides, code

X. Zhang, Y. Chang, T. Lu, K. Zhang, and M. Chen, “Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric,” 2023 IEEE/ACM 23rd International Symposium on Cluster, Cloud and Internet Computing (CCGrid), Bangalore, India, 2023, pp. 25-35, doi: 10.1109/CCGrid57682.2023.00013. paper, slides, lightning talk, code

Qi Le, Chang Yisong, Chen Yuxiao, Zhang Xu, Chen Mingyu, Bao Yungang, Zhang Ke. A System-Level Platform with SoC-FPGA for RISC-V Hardware-Software Integration[J]. Journal of Computer Research and Development, 2023, 60(6): 1204-1215. doi: 10.7544/issn1000-1239.202330060

2022 X. Zhang, Y. Chang, T. Lu, K. Liu, K. Zhang, and M. Chen, “GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing,” 2022 International Conference on Field-Programmable Technology (ICFPT), Hong Kong, 2022, pp. 1-2, doi: 10.1109/ICFPT56656.2022.9974189. paper, slides, lightning talk

Luming Wang, Xu Zhang, Tianyue Lu, Mingyu Chen, “Asynchronous memory access unit for general purpose processors”, BenchCouncil Transactions on Benchmarks, Standards and Evaluations, 2 (2022) 100061, DOI: https://doi.org/10.1016/j.tbench.2022.100061

2021 Luming Wang, Xu Zhang, Tianyue Lu, Mingyu Chen, ”Asynchronous Memory Access Unit for General Purpose Processors”, arxiv.org:2112.13306

2020 ZHANG Xu, CHANG Yisong, ZHANG Ke, et al. Design and implementation of a novel off-chip memory access path for graph computing[J]. Journal of National University of Defense Technology, 2020, 42(2):13-22. paper

Occupation

Teaching assistant of Computer Organization and Design course (B0911007Y)

Awards

Huawei Doctor Award (given by Huawei in 2023)

Outstanding Student Award (given by UCAS in 2021)

Fintech Master Award (given by E-Fund in 2020)

Acknowledgment

Currently, I am engaged in close collaboration with Prof. Ke Zhang, A.P. Yisong Chang, and A.P. Tianyue Lu on my research endeavors. To conduct my experiments and drive researches forward, We have established a robust infrastructure using the FPGA cloud platform SERVE and the powerful hybrid memory trace toolkit HMTT.

The SERVE platform provids us with access to FPGA resources in the cloud. Leveraging the scalability and parallel processing capabilities of FPGAs, we can implement distributed multi-FPGA platform and optimize complex algorithms, enabling us to tackle challenging research problems.

We rely on the HMTT toolkit offering capabilities for capturing and analyzing memory traces. By leveraging a DIMM-snooping mechanism and software-controlled tracing, HMTT enables us to gain deep insights into memory behavior and correlate it with high-level events.